Flash MemoryMPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 637— Each AHB input port provides configurable and independent read buffering and page prefetchsupport for banks 0 and 2— Each AHB input port includes four page read buffers (each 128 bits wide) and a prefetchcontroller to support single-cycle read responses (zero AHB data phase wait-states) for hits inthe buffers. The buffers implement a least-recently-used replacement algorithm to maximizeperformance.— Each AHB input port interfaces to the optional data flash (bank1) includes a 128-bit register totemporarily hold a single flash page. This logic supports single-cycle read responses (zeroAHB data phase wait-states) for accesses that hit in the holding register. There is no support forprefetching associated with this bank.• Programmable response for read-while-write sequences including support for stall-while-write,optional stall notification interrupt, optional flash operation abort, and optional abort notificationinterrupt• Separate and independent configurable access timing (common settings for banks 0 and 2, separatesettings for bank1) to support use across a wide range of platforms and frequencies• Support of address-based read access timing for emulation of other memory types• Support for reporting of single- and multi-bit flash ECC events• Typical operating configuration loaded into programming model by system resetFigure 17-43 shows a simplified block diagram of the PFLASH2P_LCA memory controller.
