Deserial Serial Peripheral Interface (DSPI)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 315Table 11-21 shows an example of the computed after SCK delay.11.8.4.4 Delay after transfer (tDT)The delay after transfer is the length of time between negation of the CSx signal for a frame and theassertion of the CSx signal for the next frame. The PDT and DT fields in the DSPIx_CTARn registersselect the delay after transfer.Refer to Figure 11-14 for an illustration of the delay after transfer.The following formula expresses the PDT/DT/delay after transfer relationship:Table 11-22 shows an example of the computed delay after transfer.When in non-continuous clock mode the tDT delay is configurable as outlined in the DSPI_CTARxregisters. When in continuous clock mode and TSB is not enabled, the delay is fixed at 1 SCK period.When in TSB and continuous mode the delay is programmed as outlined in the DSPI_CTARx registers,but in the event that the delay does not coincide with an SCK period in duration, then the delay is extendedto the next SCK active edge. Table 11-23 shows an example of how to compute the delay after transferwith the clock period of SCK defined as TSCK. The values calculated assume 1 TSCK period = 4 ipg_clk.Table 11-21. After SCK delay computation examplePASC Prescaler value ASC Scaler value fSYS After SCK delay0b01 3 0b0100 32 100 MHz 0.96 sTable 11-22. Delay after transfer computation examplePDT Prescaler value DT Scaler value fSYS Delay after transfer0b01 3 0b1110 32768 100 MHz 0.98 mstDT = fSYSDT PDT1
