Stepper Stall Detect (SSD)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 117336.4.1.4.3 DC Offset CancellationDue to deviations from the mid point of the analog supply voltages and other effects in the hardware of theanalog blocks a DC offset may be introduced into the output of the -modulator. As a consequence ofsuch a DC offset the value obtained in the integration accumulator would depend from the ‘direction’ ofthe integration (e.g. accumulator increment for positive back EMF in clockwise movement). The DC offsetcancellation implemented in the SSD block can eliminate (or at least reduce) the influence of such a DCoffset:When active the DC offset cancellation reverts two internal settings in the SSD block during theintegration phase of the current BIS:• The input into the analog block controlling the integration polarity which sets the switch conditionstate (third column in Table 36-12):Initial value (when the integration starts at step 5 in Section 36.4.2.2, Details of the SSDMeasurement) is the bit value given in the ITGDIR register in the CONTROL register.• The output of the -modulator being applied to the integration accumulator (ITGACC register):Initially it is applied without change to the integration accumulator.As a result the switch conditions in the analog circuitry change the direction of the voltage representingthe back EMF measured by the -modulator. But the change direction of the ITGACC register ismaintained because the interpretation of the -modulator output is reverted, too.The offset cancellation is implemented as an additional counter running during the integration phase withthe same clock setting like the DCNT register. The preset value for this counter is derived from theITGCNTLD register by shifting right by 0, 1, 2 or 3 bits, depending from the OFFCNC bit setting. Clearingall the OFFCNC bits obviously disables the offset cancellation completely. Note that increasing thenumber of flips improves the offset cancellation because the different polarities are distributed equallyover the complete integration phase (if ITGCNTLD can be divided by the appropriate number). Refer toFigure 36-10 for more details.Table 36-14. ITGACC update clock vs. bus clock—recommended settings11 Numbers rounded appropriatelyBus Clock 40 MHz 64 MHz 80 MHzACDIV 3’b010 3’b011 3’b011 3’b100 3’b011 3’b100Divider factor 32 64 64 128 64 128Sampling frequency 1.25 MHz 625 kHz 1.00 MHz 500 kHz 1.25 MHz 625 kHzUpdate interval 0.8 s 1.6 s 1.00 s 2.00 s 0.8 s 1.6 s
