Chapter 2 Port Integration Module (S12ZVMBPIMV3)MC9S12ZVMB Family Reference Manual Rev. 1.3104 NXP Semiconductors2.3.4.13 Port L ADC Direct Register (PTADIRL)2.3.4.14 Port L Digital Input Enable Register (DIENL)Address 0x033B Access: User read/write(1)1. Read: AnytimeWrite: Anytime7 6 5 4 3 2 1 0R 0 0 0 0 0 PTADIRL2 PTADIRL1 PTADIRL0WReset 0 0 0 0 0 0 0 0Figure 2-35. Port L ADC Direct Register (PTADIRL)Table 2-39. PTADIRL Register Field DescriptionsField Description2-0PTADIRL2-0Port L ADC Direct Connection —This bit connects the analog input signal directly to the ADC channel bypassing the voltage divider. This bit takeseffect only in analog mode (PTAENL=1).1 Input pin directly connected to ADC channel0 Input voltage divider active on analog input to ADC channelAddress 0x33C Access: User read/write(1)1. Read: AnytimeWrite: Anytime7 6 5 4 3 2 1 0R 0 0 0 0 0 DIENL2 DIENL1 DIENL0WReset 0 0 0 0 0 0 0 0Figure 2-36. Port L Digital Input Enable Register (DIENL)Table 2-40. DIENL Register Field DescriptionsField Description2-0DIENL2-0Digital Input Enable Port L — Input buffer controlThis bit controls the HVI digital input function. If set to 1 the input buffer is enabled and the HVI pin can be used withthe digital function. If the analog input function is enabled (PTAENL=1) the input buffer of the selected HVI pin isforced off(1) in run mode and is released to be active in stop mode (2) only if DIENL=1.1 Associated pin digital input is enabled if not used as analog input in run mode10 Associated pin digital input is disabled11. Refer to PTTEL bit description in Section 2.3.4.15, “Port L ADC Connection Enable Register (PTAENL) for an override condition.2. “Stop mode” is limited to RPM; refer to Table 2-47.
