Chapter 3 Memory Mapping Control (S12ZMMCV1)MC9S12ZVMB Family Reference Manual Rev. 1.3124 NXP SemiconductorsTable 3-6. MMCCCRH and MMCCCRL Field Descriptions3.3.2.4 Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL)Figure 3-7. Captured S12ZCPU Program Counter (MMCPCH, MMCPCM, MMCPCL)Read: AnytimeWrite: NeverField Description7 (MMCCCRH)CPUUS12ZCPU User State Flag — This bit shows the state of the user/supervisor mode bit in the S12ZCPU’s CCRat the time the access violation has occurred. The S12ZCPU user state flag is read-only; it will be automaticallyupdated when the next error condition is flagged through the MMCEC register. This bit is undefined if the errorcode registers (MMCECn) are cleared.6 (MMCCCRL)CPUXS12ZCPU X-Interrupt Mask— This bit shows the state of the X-interrupt mask in the S12ZCPU’s CCR at thetime the access violation has occurred. The S12ZCPU X-interrupt mask is read-only; it will be automaticallyupdated when the next error condition is flagged through the MMCEC register. This bit is undefined if the errorcode registers (MMCECn) are cleared.4 (MMCCCRL)CPUIS12ZCPU I-Interrupt Mask— This bit shows the state of the I-interrupt mask in the CPU’s CCR at the time theaccess violation has occurred. The S12ZCPU I-interrupt mask is read-only; it will be automatically updatedwhen the next error condition is flagged through the MMCEC register. This bit is undefined if the error coderegisters (MMCECn) are cleared.Address: 0x0085 (MMCPCH)7 6 5 4 3 2 1 0R CPUPC[23:16]WReset 0 0 0 0 0 0 0 0Address: 0x0086 (MMCPCM)7 6 5 4 3 2 1 0R CPUPC[15:8]WReset 0 0 0 0 0 0 0 0Address: 0x0087 (MMCPCL)7 6 5 4 3 2 1 0R CPUPC[7:0]WReset 0 0 0 0 0 0 0 0
