Chapter 9 Analog-to-Digital ConverterMC9S12ZVMB Family Reference Manual Rev. 1.3308 NXP Semiconductors5RSTARestart Event (Restart from Top of Command Sequence List) — This bit indicates that a Restart Event isexecuted. The ADC loads the conversion command from top of the active Sequence Command List when noconversion or conversion sequence is ongoing. This bit is cleared when the first conversion command of thesequence from top of active Sequence Command List has been loaded into the ADCCMD register.This bit can only be set if bit ADC_EN is set.This bit is cleared if bit ADC_EN is clear.Data Bus Control:This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0].Writing a value of 1’b0 does not clear the flag.Writing a one to this bit does not clear it but causes an overrun if the bit has already been set. See alsoSection 9.6.3.2.6, “Conversion flow control in case of conversion sequence control bit overrun scenarios for moredetails.Internal Interface Control:This bit can be controlled via the internal interface Signal “Restart” if access control is configured accordingly viaACC_CFG[1:0]. After being set an additional request via internal interface Signal “Restart“ causes an overrun.See conversion flow control in case of overrun situations for more details.General:In conversion flow control mode “Trigger Mode” when bit RSTA gets set bit TRIG is set simultaneously if one ofthe following has been executed:- “End Of List” command type has been executed or is about to be executed- Sequence Abort Event0 Continue with commands from active Sequence Command List.1 Restart from top of active Sequence Command List.4LDOKLoad OK for alternative Command Sequence List — This bit indicates if the preparation of the alternativeSequence Command List is done and Command Sequence List must be swapped with the Restart Event. Thisbit is cleared when bit RSTA is set (Restart Event executed) and the Command Sequence List got swapped.This bit can only be set if bit ADC_EN is set.This bit is cleared if bit ADC_EN is clear.This bit is forced to zero if bit CSL_BMOD is clear.Data Bus Control:This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0].Writing a value of 1’b0 does not clear the flag.To set bit LDOK the bits LDOK and RSTA must be written simultaneously.After being set this bit can not be cleared by writing a value of 1’b1. See also Section 9.6.3.2.6, “Conversion flowcontrol in case of conversion sequence control bit overrun scenarios for more details.Internal Interface Control:This bit can be controlled via the internal interface Signal “LoadOK” and “Restart” if access control is configuredaccordingly via ACC_CFG[1:0]. With the assertion of Interface Signal “Restart” the interface Signal “LoadOK” isevaluated and bit LDOK set accordingly (bit LDOK set if Interface Signal “LoadOK” asserted when InterfaceSignal “Restart” asserts).General:Only in “Restart Mode” if a Restart Event occurs without bit LDOK being set the error flag LDOK_EIF is set exceptwhen the respective Restart Request occurred after or simultaneously with a Sequence Abort Request.The LDOK_EIF error flag is also not set in “Restart Mode” if the first Restart Event occurs after:- ADC got enabled- Exit from Stop Mode- ADC Soft-Reset0 Load of alternative list done.1 Load alternative list.Table 9-10. ADCFLWCTL Field Descriptions (continued)Field Description
