Chapter 2 Port Integration Module (S12ZVMBPIMV3)MC9S12ZVMB Family Reference Manual Rev. 1.374 NXP SemiconductorsTable 2-5. Port T Pin Functions and PrioritiesPort Pin Pin Function& Priority I/O Description RoutingRegister BitFunc.afterResetT PT7 IOC1_3 I/O TIM1 channel 3 T1IC3RR GPIOPTT[7] I/O GPIO —PT6 IOC1_2 I/O TIM1 channel 2 T1IC2RR,T1OC2RRPTT[6] I/O GPIO —PT5 IOC1_1 I/O TIM1 channel 1 T1IC1RR,T1OC1RRPTT[5] I/O GPIO —PT4 IOC1_0 I/O TIM1 channel 0 T1IC0RRPTT[4] I/O GPIO —PT3 IOC0_3 I/O TIM0 channel 3 T0IC3RR1-0PTT[3] I/O GPIO —PT2(1)1. High current capable low-side output with over-current interrupt and protection for all sources (see 2.4.5.3/2-110)ECLK O Free-running clock —FAULT5 I PMF fault FAULT5RR(LP0RXD) O LINPHY0/HVPHY0 receive output S0L0RR2-0(PWM3) O PMF channel 3 P0C3RRIOC0_2 I/O TIM0 channel 2 T0IC2RRPTT[2]/NGPIOI/O GPIO —PT1 (LP0DR1) O LPTXD0 direct control by LP0DR[LP0DR1] S0L0RR2-0TXD1 I/O SCI1 transmit SCI1RR(TXD0) I/O SCI0 transmit S0L0RR2-0MISO0 I/O SPI0 master in/slave out —(PWM2) O PMF channel 2 P0C2RRIOC0_1 I/O TIM0 channel 1 —PTT[1] I/O GPIO —PT0 XIRQ (2)2. The interrupt is enabled by clearing the X mask bit in the CPU CCR. The pin is forced to input upon first clearing of the X bit andis held in this state until reset. A stop or wait recovery using XIRQ with the X bit set is not available.I Non-maskable level-sensitive interrupt —RXD1 I SCI1 receive SCI1RR(RXD0) I SCI0 receive S0L0RR2-0MOSI0 I/O SPI0 master out/slave in —IOC0_0 I/O TIM0 channel 0 —PTT[0] I/O GPIO —
