Chapter 14 Serial Communication Interface (S12SCIV6)MC9S12ZVMB Family Reference Manual Rev. 1.3486 NXP Semiconductors14.3.2.3 SCI Alternative Status Register 1 (SCIASR1)Read: Anytime, if AMAP = 1Write: Anytime, if AMAP = 114.3.2.4 SCI Alternative Control Register 1 (SCIACR1)Read: Anytime, if AMAP = 1Write: Anytime, if AMAP = 1Module Base + 0x00007 6 5 4 3 2 1 0R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIFWReset 0 0 0 0 0 0 0 0= Unimplemented or ReservedFigure 14-6. SCI Alternative Status Register 1 (SCIASR1)Table 14-6. SCIASR1 Field DescriptionsField Description7RXEDGIFReceive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.0 No active receive on the receive input has occurred1 An active edge on the receive input has occurred2BERRVBit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled anda mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.0 A low input was sampled, when a high was expected1 A high input reassembled, when a low was expected1BERRIFBit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the valuesampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set aninterrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.0 No mismatch detected1 A mismatch has occurred0BKDIFBreak Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal isreceived. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writinga “1” to it.0 No break signal was received1 A break signal was receivedModule Base + 0x00017 6 5 4 3 2 1 0R RXEDGIE 0 0 0 0 0 BERRIE BKDIEWReset 0 0 0 0 0 0 0 0= Unimplemented or ReservedFigure 14-7. SCI Alternative Control Register 1 (SCIACR1)
