Chapter 9 Analog-to-Digital ConverterMC9S12ZVMB Family Reference Manual Rev. 1.3306 NXP Semiconductors9.5.2.6 ADC Conversion Flow Control Register (ADCFLWCTL)Bit set and bit clear instructions should not be used to access this register.When the ADC is enabled the bits of ADCFLWCTL register can be modified after a latency time of threeBus Clock cycles.All bits are cleared if bit ADC_EN is clear or via ADC soft-reset.Read: AnytimeWrite:• Bits SEQA, TRIG, RSTA, LDOK can only be set if bit ADC_EN is set.• Writing 1’b0 to any of these bits does not have an effectTiming considerations (Trigger Event - channel sample start) depending on ADC mode configuration:• Restart ModeWhen the Restart Event has been processed (initial command of current CSL is loaded) it takes twoBus Clock cycles plus two ADC conversion clock cycles (pump phase) from the Trigger Event (bitTRIG set) until the select channel starts to sample.During a conversion sequence (back to back conversions) it takes five Bus Clock cycles plus twoADC conversion clock cycles (pump phase) from current conversion period end until the newlyselected channel is sampled in the following conversion period.• Trigger ModeWhen a Restart Event occurs a Trigger Event is issued simultaneously. The time required to processthe Restart Event is mainly defined by the internal read data bus availability and therefore can vary.In this mode the Trigger Event is processed immediately after the Restart Event is finished and bothconversion flow control bits are cleared simultaneously. From de-assert of bit TRIG until samplingbegins five Bus Clock cycles are required. Hence from occurrence of a Restart Event until channelsampling it takes five Bus Clock cycles plus an uncertainty of a few Bus Clock cycles.For more details regarding the sample phase please refer to Section 9.6.2.2, “Sample and Hold Machine with Sample BufferAmplifier.Module Base + 0x00057 6 5 4 3 2 1 0R SEQA TRIG RSTA LDOK 0 0 0 0WReset 0 0 0 0 0 0 0 0= Unimplemented or ReservedFigure 9-9. ADC Conversion Flow Control Register (ADCFLWCTL)
