Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11)MC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 239Read: AnytimeWrite: Refer to each bit for individual write conditionsModule Base + 0x00077 6 5 4 3 2 1 0R RTIF 0 0 LOCKIF LOCK 0 OSCIF UPOSCWReset 0 0 0 0 0 0 0 0= Unimplemented or ReservedFigure 8-10. S12CPMU_UHV_V11 Flags Register (CPMUIFLG)Table 8-5. CPMUIFLG Field DescriptionsField Description7RTIFReal Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writinga 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.0 RTI time-out has not yet occurred.1 RTI time-out has occurred.4LOCKIFPLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared bywriting a 1. Writing a 0 has no effect. If enabled (LOCKIE=1), LOCKIF causes an interrupt request.0 No change in LOCK bit.1 LOCK bit has changed.3LOCKLock Status Bit — LOCK reflects the current state of PLL lock condition. Writes have no effect. While PLL isunlocked (LOCK=0) f PLL is f VCO / 4 to protect the system from high core clock frequencies during the PLLstabilization time tlock .0 VCOCLK is not within the desired tolerance of the target frequency.f PLL = f VCO /4.1 VCOCLK is within the desired tolerance of the target frequency.f PLL = f VCO /(POSTDIV+1).1OSCIFOscillator Interrupt Flag — OSCIF is set to 1 when UPOSC status bit changes. This flag can only be clearedby writing a 1. Writing a 0 has no effect. If enabled (OSCIE=1), OSCIF causes an interrupt request.0 No change in UPOSC bit.1 UPOSC bit has changed.0UPOSCOscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. Entering Full StopMode UPOSC is cleared.0 The oscillator is off or oscillation is not qualified by the PLL.1 The oscillator is qualified by the PLL.
