Chapter 15 Serial Peripheral Interface (S12SPIV5)MC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 523Table 15-4. SPICR2 Field DescriptionsField Description6XFRWTransfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRLbecomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH andSPIDRL form a 16-bit data register. Please refer to Section 15.3.2.4, “SPI Status Register (SPISR) forinformation about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, achange of this bit will abort a transmission in progress and force the SPI system into idle state.0 8-bit Transfer Width (n = 8) (1)1 16-bit Transfer Width (n = 16) 11. n is used later in this document as a placeholder for the selected transfer width.4MODFENMode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode andMODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as aninput regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pinconfiguration, refer to Table 15-3. In master mode, a change of this bit will abort a transmission in progress andforce the SPI system into idle state.0 SS port pin is not used by the SPI.1 SS port pin with MODF feature.3BIDIROEOutput Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output bufferof the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the outputbuffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0set, a change of this bit will abort a transmission in progress and force the SPI into idle state.0 Output buffer disabled.1 Output buffer enabled.1SPISWAISPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.0 SPI clock operates normally in wait mode.1 Stop SPI clock generation when in wait mode.0SPC0Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 15-5. In mastermode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.Table 15-5. Bidirectional Pin ConfigurationsPin Mode SPC0 BIDIROE MISO MOSIMaster Mode of OperationNormal 0 X Master In Master OutBidirectional 1 0 MISO not used by SPI Master In1 Master I/OSlave Mode of OperationNormal 0 X Slave Out Slave InBidirectional 1 0 Slave In MOSI not used by SPI1 Slave I/O
