Chapter 2 Port Integration Module (S12ZVMBPIMV3)MC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 75Table 2-6. Port P Pin Functions and PrioritiesTable 2-7. Port L Pin Functions and PrioritiesPort Pin Pin Function& Priority I/O Description RoutingRegister BitFunc.afterResetP PP1 (FAULT5) I PMF fault FAULT5RR GPIOSCK0 I/O SPI0 serial clock —PWM5 O PMF channel 5 P0C5RRPTP[1]/KWP[1]I/O GPIO with pin-interrupt and key-wakeup —PP0(1)1. High current capable high-side output with over-current interrupt and protection for all sources (see 2.4.5.3/2-110)IRQ I Maskable level- or falling edge-sensitiveinterrupt—(LP0TXD) I LINPHY0/HVPHY0 transmit input S0L0RR2-0PTURE O PTU reload event with over-current interrupt;high-current capable (20 mA)—PWM4 O PMF channel 4 with over-current interrupt;high-current capable (20 mA)P0C4RRPTP[0]/KWP[0]/EVDDI/O General-purpose; with interrupt and wakeupSwitchable external power supply output withover-current interrupt; high-current capable(20 mA)—Port Pin Pin Function& Priority I/O Description RoutingRegister BitFunc.afterResetL PL2 IOC1_2 I TIM1 input capture channel 2 T1IC2RR HVIAN11 I ADC0 analog input AN11PTIL[2]/KWL[2]I HVI with pin-interrupt and key-wakeup —PL1 IOC1_1 I TIM1 input capture channel 1 T1IC1RRAN10 I ADC0 analog input AN10PTIL[1]/KWL[1]I HVI with pin-interrupt and key-wakeup —PL0 IOC1_0 I TIM1 input capture channel 0 T1IC0RRAN9 I ADC0 analog input AN9PTIL[0]/KWL[0]I HVI with pin-interrupt and key-wakeup —
