Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4)MC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 41712.3.2.25 PMF Frequency Control B Register (PMFFQCB)1. Read: Anytime. Returns zero if MTG is clear.Write: Anytime if MTG is set.GLDOKB and RSTRTB cannot be modified after the WP bit is set.Table 12-29. PMFENCB Field DescriptionsField Description7PWMENBPWM Generator B Enable — If MTG is clear, this bit reads zero and cannot be written.If MTG is set, this bit when set enables the PWM generator B and the PWM2 and PWM3 outputs. WhenPWMENB is clear, PWM generator B is disabled, and the PWM2 and PWM3 outputs are in their inactive statesunless the corresponding OUTCTL bits are set.After setting this bit a reload event is generated at the beginning of the PWM cycle.0 PWM generator B and PWM2–3 outputs disabled unless the respective OUTCTL bit is set1 PWM generator B and PWM2–3 outputs enabled6GLDOKBGlobal Load Okay B — When this bit is set, a PMF external global load OK defined on device level replaces thefunction of LDOKB. This bit cannot be modified after the WP bit is set.0 LDOKB controls double reload of buffered registers1 PMF external global load OK controls reload of double buffered registers2RSTRTBRestart Generator B — When this bit is set, PWM generator B will be restarted at the next commutation event.This bit cannot be modified after the WP bit is set.0 No PWM generator B restart at the next commutation event1 PWM generator B restart at the next commutation event1LDOKBLoad Okay B — If MTG is clear, this bit reads zero and cannot be written.If MTG is set, this bit loads the PRSCB bits, the PMFMODB register and the PMFVAL2-3 registers into a set ofbuffers. The buffered prescaler divisor B, PWM counter modulus B value, PWM2–3 pulse widths take effect atthe next PWM reload.Set LDOKB by reading it when it is logic zero and then writing a logic one to it. LDOKB is automatically clearedafter the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Resetclears LDOKB.0 Do not load new modulus B, prescaler B, and PWM2–3 values1 Load prescaler B, modulus B, and PWM2–3 valuesNote: Do not set PWMENB bit before setting the LDOKB bit and do not clear the LDOKB bit at the same time assetting the PWMENB bit.0PWMRIEBPWM Reload Interrupt Enable B — If MTG is clear, this bit reads zero and cannot be written.If MTG is set, this bit enables the PWMRFB flag to generate CPU interrupt requests.0 PWMRFB CPU interrupt requests disabled1 PWMRFB CPU interrupt requests enabledAddress: Module Base + 0x0029 Access: User read/write(1)1. Read: Anytime. Returns zero if MTG is clear.Write: Anytime if MTG is set.7 6 5 4 3 2 1 0R LDFQB HALFB PRSCB PWMRFBWReset 0 0 0 0 0 0 0 0Figure 12-30. PMF Frequency Control B Register (PMFFQCB)
