Chapter 19 Flash Module (S12ZFTMRZ)MC9S12ZVMB Family Reference Manual Rev. 1.3632 NXP SemiconductorsAll flags in the FERSTAT register are readable and only writable to clear the flag.19.3.2.9 P-Flash Protection Register (FPROT)The FPROT register defines which P-Flash sectors are protected against program and erase operations.Offset Module Base + 0x00077 6 5 4 3 2 1 0R 0 0 0 0 0 0 DFDF SFDIFWReset 0 0 0 0 0 0 0 0= Unimplemented or ReservedFigure 19-12. Flash Error Status Register (FERSTAT)Table 19-18. FERSTAT Field DescriptionsField Description1DFDFDouble Bit Fault Detect Flag — The setting of the DFDF flag indicates that a double bit fault was detected inthe stored parity and data bits during a Flash array read operation or that a Flash array read operation returninginvalid data was attempted on a Flash block that was under a Flash command operation. (1) The DFDF flag iscleared by writing a 1 to DFDF. Writing a 0 to DFDF has no effect on DFDF.(2)0 No double bit fault detected1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while commandrunning. See Section 19.4.3, “Flash Block Read Access” for details1. In case of ECC errors the corresponding flag must be cleared for the proper setting of any further error, i.e. any new error willonly be indicated properly when DFDF and/or SFDIF are clear at the time the error condition is detected.2. There is a one cycle delay in storing the ECC DFDF and SFDIF fault flags in this register. At least one NOP is required aftera flash memory read before checking FERSTAT for the occurrence of ECC errors.0SFDIFSingle Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flagindicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operationor that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flashcommand operation. The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect onSFDIF.0 No single bit fault detected1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attemptedwhile command runningOffset Module Base + 0x00087 6 5 4 3 2 1 0R FPOPEN RNV6 FPHDIS FPHS[1:0] FPLDIS FPLS[1:0]WReset F (1)1. Loaded from Flash configuration field, during reset sequence.F1 F 1 F 1 F1 F 1 F1 F 1= Unimplemented or ReservedFigure 19-13. Flash Protection Register (FPROT)
