Chapter 5 Background Debug Controller (S12ZBDCV2)MC9S12ZVMB Family Reference Manual Rev. 1.3146 NXP SemiconductorsAccesses to the internal memory map are not possible when the internal device clocks are disabled. Thusattempted accesses to memory mapped resources are suppressed and the NORESP flag is set. Resourcescan be accessed again by the next command received following exit from Stop mode.A BACKGROUND command issued whilst in stop mode remains pending internally until the deviceleaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND ispending, set the ILLCMD flag because the device is not yet in active BDM.If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stopexception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the hostattempts further communication before the ACK pulse generation then the OVRUN bit is set.STOP Mode With BDC Enabled And BDCCIS SetIf the BDC is enabled and BDCCIS is set, then the BDC prevents core clocks being disabled in stop mode.This allows BDC communication, for access of internal memory mapped resources, but not CPU registers,to continue throughout stop mode.A BACKGROUND command issued whilst in stop mode remains pending internally until the deviceleaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND ispending, set the ILLCMD flag because the device is not yet in active BDM.If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stopexception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the hostattempts further communication before the ACK pulse generation then the OVRUN bit is set.5.1.3.3.2 Wait ModeThe device enters wait mode when the CPU starts to execute the WAI instruction. The second part of theWAI instruction (return from wait mode) can only be performed when an interrupt occurs. Thus onentering wait mode the CPU is in the middle of the WAI instruction and cannot permit access to CPUinternal resources, nor allow entry to active BDM. Thus only commands classified as Non-Intrusive orAlways-Available are possible in wait mode.On entering wait mode, the WAIT flag in BDCCSR is set. If the ACK handshake protocol is enabled thenthe first ACK generated after WAIT has been set is a long-ACK pulse. Thus the host can recognize a waitmode occurrence. The WAIT flag remains set and cannot be cleared whilst the device remains in waitmode. After the device leaves wait mode the WAIT flag can be cleared by writing a “1” to it.A BACKGROUND command issued whilst in wait mode sets the NORESP bit and the BDM activerequest remains pending internally until the CPU leaves wait mode due to an interrupt. The device thenenters BDM with the PC pointing to the address of the first instruction of the ISR.With ACK disabled, further Non-Intrusive or Always-Available commands are possible, in this pendingstate, but attempted Active-Background commands set NORESP and ILLCMD because the BDC is not inactive BDM state.With ACK enabled, if the host attempts further communication before the ACK pulse generation then theOVRUN bit is set.
