Chapter 12 Pulse Width Modulator with Fault Protection (PMF15B6CV4)MC9S12ZVMB Family Reference Manual Rev. 1.3414 NXP Semiconductors12.3.2.20 PMF Frequency Control A Register (PMFFQCA)1LDOKALoad Okay A — When MTG is clear, this bit allows loads of the PRSCA bits, the PMFMODA register, and thePMFVAL0-5 registers into a set of buffers. The buffered prescaler A divisor, PWM counter modulus A value, andall PWM pulse widths take effect at the next PWM reload.When MTG is set, this bit allows loads of the PRSCA bits, the PMFMODA register, and the PMFVAL0–1 registersinto a set of buffers. The buffered prescaler divisor A, PWM counter modulus A value, and PWM0–1 pulse widthstake effect at the next PWM reload.Set LDOKA by reading it when it is logic zero and then writing a logic one to it. LDOKA is automatically clearedafter the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Resetclears LDOKA.0 Do not load new modulus A, prescaler A, and PWM0–1 (2–5 if MTG = 0) values1 Load prescaler A, modulus A, and PWM0–1 (2–5 if MTG = 0) valuesNote: Do not set PWMENA bit before setting the LDOKA bit and do not clear the LDOKA bit at the same time assetting the PWMENA bit.0PWMRIEAPWM Reload Interrupt Enable A — This bit enables the PWMRFA flag to generate CPU interrupt requests.0 PWMRFA CPU interrupt requests disabled1 PWMRFA CPU interrupt requests enabledAddress: Module Base + 0x0021 Access: User read/write(1)1. Read: AnytimeWrite: Anytime7 6 5 4 3 2 1 0R LDFQA HALFA PRSCA PWMRFAWReset 0 0 0 0 0 0 0 0Figure 12-25. PMF Frequency Control A Register (PMFFQCA)Table 12-26. PMFFQCA Field DescriptionsField Description7–4LDFQA[3:0]Load Frequency A — This field selects the PWM load frequency according to Table 12-27. SeeSection 12.4.12.3, “Load Frequency” for more details.Note: The LDFQA field takes effect when the current load cycle is complete, regardless of the state of theLDOKA bit or global load OK. Reading the LDFQA field reads the buffered value and not necessarily thevalue currently in effect.3HALFAHalf Cycle Reload A — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effecton edge-aligned PWMs. It takes effect immediately. When set, reload opportunities occur also when the countermatches the modulus in addition to the start of the PWM period at count zero. See Section 12.4.12.3, “LoadFrequency” for more details.0 Half-cycle reloads disabled1 Half-cycle reloads enabledTable 12-25. PMFENCA Field Descriptions (continued)Field Description
