Chapter 15 Serial Peripheral Interface (S12SPIV5)MC9S12ZVMB Family Reference Manual Rev. 1.3528 NXP Semiconductors15.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL)Read: Anytime; read data only valid when SPIF is setWrite: AnytimeThe SPI data register is both the input and output register for SPI data. A write to this registerallows data to be queued and transmitted. For an SPI configured as a master, queued data istransmitted immediately after the previous transmission has completed. The SPI transmitter emptyflag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data.Received data in the SPIDR is valid when SPIF is set.If SPIF is cleared and data has been received, the received data is transferred from the receive shiftregister to the SPIDR and SPIF is set.If SPIF is set and not serviced, and a second data value has been received, the second received datais kept as valid data in the receive shift register until the start of another transmission. The data inthe SPIDR does not change.If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start ofa third transmission, the data in the receive shift register is transferred into the SPIDR and SPIFremains set (see Figure 15-9).If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of athird transmission, the data in the receive shift register has become invalid and is not transferredinto the SPIDR (see Figure 15-10).Module Base +0x00047 6 5 4 3 2 1 0R R15 R14 R13 R12 R11 R10 R9 R8W T15 T14 T13 T12 T11 T10 T9 T8Reset 0 0 0 0 0 0 0 0Figure 15-7. SPI Data Register High (SPIDRH)Module Base +0x00057 6 5 4 3 2 1 0R R7 R6 R5 R4 R3 R2 R1 R0W T7 T6 T5 T4 T3 T2 T1 T0Reset 0 0 0 0 0 0 0 0Figure 15-8. SPI Data Register Low (SPIDRL)
