Chapter 1 Device Overview MC9S12ZVMB-FamilyMC9S12ZVMB Family Reference Manual Rev. 1.362 NXP SemiconductorsAssuming first quadrant operation, forward accelerating operation, the applied voltage at node A mustexceed the applied voltage at node B (Figure 1-8). Thus the PWM0 duty cycle must exceed the PWM2duty cycle.The PWM duty cycle of PWM0 defines the voltage at the first power stage branch.The PWM duty cycle of PWM2 defines the voltage at the second power stage branch.Modulating the PWM duty cycle every period using the function F PWM then the duty cycle is expressed as:PWM0 duty-cycle = 0.5 + (0.5 * FPWM); For -1<=FPWM <= 1;PWM2 duty-cycle = 0.5 - (0.5 * F PWM)1.13.3.1 Control loop timing considerationsDelays within the separate control loop elements require consideration to ensure correct synchronization.Regarding the raw PWM signal as the starting point and stepping through the control loop stages, thefactors shown in Figure 1-10 contribute to delays within the control loop, starting with the deadtimeinsertion, going through the external FETs and back into the internal ADC measurements of externalvoltages and currents.Figure 1-10. Control loop delay overviewThe PWM deadtime (TDEAD_X) is an integral number of bus clock cycles, configured by the PMFdeadtime registers.The GDU propagation delays (tdelon, tdeloff) are specified in the electrical parameter Table E-1.The FET turn on times (tGHGON ) are load dependent but are specified for particular loads in the electricalparameter Table E-1.The current sense amplifier delay is highly dependent on external components.The ADC delay until a result is available is specified as the conversion period NCONV in Table C-1.PWM withPWM basePWM cycledeadtimeGDUpropagationFETturn onCurrent sensesettling timeADC delayT DEAD_xtdelontHGON(tcslsst)
