Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11)MC9S12ZVMB Family Reference Manual Rev. 1.3226 NXP Semiconductorsto CSAD bit description for details) occurs when entering or exiting (Full, Pseudo) Stop Mode.When bit CSAD is clear the ACLK clock source is on for the COP during Full Stop Mode andCOP is operating.During Full Stop Mode the RTI counter halts.After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK(PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0,RTIOSCSEL=0).• Pseudo Stop Mode (PSTP = 1 and OSCE=1)External oscillator (XOSCLCP) continues to run.— If COPOSCSEL1=0:If the respective enable bits are set (PCE=1 and PRE=1) the COP and RTI will continue to runwith a clock derived from the oscillator clock.The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.— If COPOSCSEL1=1:If the respective enable bit for the RTI is set (PRE=1) the RTI will continue to run with a clockderived from the oscillator clock.The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). DuringPseudo Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active)depending on the setting of bit CSAD. When bit CSAD is set the ACLK for the COP is stoppedduring Pseudo Stop Mode and COP continues to operate after exit from Pseudo Stop Mode.For this COP configuration (ACLK clock source, CSAD set) a latency time (please refer toCSAD bit description for details) occurs when entering or exiting (Pseudo, Full) Stop Mode.When bit CSAD is clear the ACLK clock source is on for the COP during Pseudo Stop Modeand COP is operating.The clock configuration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged.NOTEWhen starting up the external oscillator (either by programming OSCE bitto 1 or on exit from Full Stop Mode with OSCE bit already 1) the softwaremust wait for a minimum time equivalent to the startup-time of the externaloscillator tUPOSC before entering Pseudo Stop Mode.8.1.2.4 Freeze Mode (BDM active)For S12CPMU_UHV_V11 Freeze Mode is the same as Run Mode except for RTI and COP which can befrozen in Active BDM Mode with the RSBCK bit in the CPMUCOP register. After exiting BDM ModeRTI and COP will resume its operations starting from this frozen status.Additionally the COP can be forced to the maximum time-out period in Active BDM Mode. For detailsplease see also the RSBCK and CR[2:0] bit description field of Table 8-14 in Section 8.3.2.12,“S12CPMU_UHV_V11 COP Control Register (CPMUCOP)
