Chapter 9 Analog-to-Digital ConverterMC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 3039.5.2.3 ADC Status Register (ADCSTS)It is important to note that if flag DBECC_ERR is set the ADC ceases operation. In order to make the ADCoperational again an ADC Soft-Reset must be issued. An ADC Soft-Reset clears bits CSL_SEL andRVL_SEL.Read: AnytimeWrite:• Bits CSL_SEL and RVL_SEL anytime if bit ADC_EN is clear or bit SMOD_ACC is set• Bits DBECC_ERR and READY not writableModule Base + 0x00027 6 5 4 3 2 1 0RCSL_SEL RVL_SELDBECC_ERR Reserved READY 0 0 0WReset 0 0 0 0 1 0 0 0= Unimplemented or ReservedFigure 9-6. ADC Status Register (ADCSTS)Table 9-6. ADCSTS Field DescriptionsField Description7CSL_SELCommand Sequence List Select bit — This bit controls and indicates which ADC Command List is active. Thisbit can only be written if ADC_EN bit is clear. This bit toggles in CSL double buffer mode when no conversion orconversion sequence is ongoing and bit LDOK is set and bit RSTA is set. In CSL single buffer mode this bit isforced to 1’b0 by bit CSL_BMOD.0 ADC Command List 0 is active.1 ADC Command List 1 is active.6RVL_SELResult Value List Select Bit — This bit controls and indicates which ADC Result List is active. This bit can onlybe written if bit ADC_EN is clear. After storage of the initial Result Value List this bit toggles in RVL double buffermode whenever the conversion result of the first conversion of the current CSL is stored or a CSL got aborted.In RVL single buffer mode this bit is forced to 1’b0 by bit RVL_BMOD.Please see also Section 9.3.1.2, “MCU Operating Modes for information regarding Result List usage in case ofStop or Wait Mode.0 ADC Result List 0 is active.1 ADC Result List 1 is active.5DBECC_ERRDouble Bit ECC Error Flag — This flag indicates that a double bit ECC error occurred during conversioncommand load or result storage and ADC ceases operation.In order to make the ADC operational again an ADC Soft-Reset must be issued.This bit is cleared if bit ADC_EN is clear.0 No double bit ECC error occurred.1 A double bit ECC error occurred.3READYReady For Restart Event Flag — This flag indicates that ADC is in its idle state and ready for a Restart Event.It can be used to verify after exit from Wait Mode if a Restart Event can be issued and processed immediatelywithout any latency time due to an ongoing Sequence Abort Event after exit from MCU Wait Mode (see also theNote in Section 9.3.1.2, “MCU Operating Modes).0 ADC not in idle state.1 ADC is in idle state.
