Chapter 11 Timer Module (TIM16B4CV3) Block DescriptionMC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 38111.3.2.12 Timer Input Capture/Output Compare Registers High and Low 0–3(TCxH and TCxL)1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes toa reserved register have no functional effect. Reads from a reserved register return zeroes.Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of thefree-running counter when a defined transition is sensed by the corresponding input capture edge detectoror to trigger an output action for output compare.Read: AnytimeWrite: Anytime for output compare function.Writes to these registers have no meaning or effect duringinput capture. All timer input capture/output compare registers are reset to 0x0000.NOTERead/Write access in byte mode for high byte should take place before lowbyte otherwise it will give a different result.Module Base + 0x0010 = TC0H0x0012 = TC1H0x0014=TC2H0x0016=TC3H0x0018=RESERVD0x001A=RESERVD0x001C=RESERVD0x001E=RESERVD15 14 13 12 11 10 9 0R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8WReset 0 0 0 0 0 0 0 0Figure 11-18. Timer Input Capture/Output Compare Register x High (TCxH)Module Base + 0x0011 = TC0L0x0013 = TC1L0x0015 =TC2L0x0017=TC3L0x0019 =RESERVD0x001B=RESERVD0x001D=RESERVD0x001F=RESERVD7 6 5 4 3 2 1 0R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0WReset 0 0 0 0 0 0 0 0Figure 11-19. Timer Input Capture/Output Compare Register x Low (TCxL)
