Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V11)MC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 285Upon detection of a status change (UPOSC) the OSCIF flag is set. Going into Full Stop Mode or disablingthe oscillator can also cause a status change of UPOSC.Any change in PLL configuration or any other event which causes the PLL lock status to be cleared leadsto a loss of the oscillator status information as well (UPOSC=0).Oscillator status change interrupts are locally enabled with the OSCIE bit.NOTELoosing the oscillator status (UPOSC=0) affects the clock configuration ofthe system1. This needs to be dealt with in application software.8.6.1.4 Low-Voltage Interrupt (LVI)In FPM the input voltage VDDA is monitored. Whenever VDDA drops below level V LVIA, the status bitLVDS is set to 1. When VDDA rises above level V LVID the status bit LVDS is cleared to 0. An interrupt,indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE= 1.8.6.1.5 HTI - High Temperature InterruptIn FPM the junction temperature T J is monitored. Whenever T J exceeds level T HTIA the status bit HTDSis set to 1. Vice versa, HTDS is reset to 0 when TJ get below level T HTID. An interrupt, indicated by flagHTIF = 1, is triggered by any change of the status bit HTDS, if interrupt enable bit HTIE = 1.8.6.1.6 Autonomous Periodical Interrupt (API)The API sub-block can generate periodical interrupts independent of the clock source of the MCU. Toenable the timer, the bit APIFE needs to be set.The API timer is either clocked by the Autonomous Clock (ACLK - trimmable internal RC oscillator) orthe Bus Clock. Timer operation will freeze when MCU clock source is selected and Bus Clock is turnedoff. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is notset.The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE iscleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. Whenthe configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggeredif interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF.The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK orAPIR[15:0], and afterwards set APIFE.The API Trimming bits ACLKTR[5:0] must be set so the minimum period equals 0.2 ms if stablefrequency is desired.See Table 8-21 for the trimming effect of ACLKTR[5:0].1. For details please refer to “8.4.6 System Clock Configurations”
