Chapter 14 Serial Communication Interface (S12SCIV6)MC9S12ZVMB Family Reference Manual Rev. 1.3514 NXP Semiconductors14.5.3.1 Description of Interrupt OperationThe SCI only originates interrupt requests. The following is a description of how the SCI makes a requestand how the MCU should acknowledge that request. The interrupt vector offset and interrupt number arechip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) andall the following interrupts, when generated, are ORed together and issued through that port.14.5.3.1.1 TDRE DescriptionThe TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCIdata register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that anew byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1with TDRE set and then writing to SCI data register low (SCIDRL).14.5.3.1.2 TC DescriptionThe TC interrupt is set by the SCI when a transmission has been completed. Transmission is completedwhen all bits including the stop bit (if transmitted) have been shifted out and no data is queued to betransmitted. No stop bit is transmitted when sending a break character and the TC flag is set (providingthere is no more data queued for transmission) when the break character has been shifted out. A TCinterrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set andno data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle(logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI dataregister low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready tobe sent.14.5.3.1.3 RDRF DescriptionThe RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. ARDRF interrupt indicates that the received data has been transferred to the SCI data register and that thebyte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one(SCISR1) and then reading SCI data register low (SCIDRL).14.5.3.1.4 OR DescriptionThe OR interrupt is set when software fails to read the SCI data register before the receive shift registerreceives the next frame. The newly acquired data in the shift register will be lost in this case, but the dataalready in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI statusregister one (SCISR1) and then reading SCI data register low (SCIDRL).BERRIF SCIASR1[1] BERRIE Active high level. Indicates that a mismatch between transmitted and received datain a single wire application has happened.BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received.Table 14-21. SCI Interrupt Sources
