Chapter 11 Timer Module (TIM16B4CV3) Block DescriptionMC9S12ZVMB Family Reference Manual Rev. 1.3NXP Semiconductors 37511.3.2.5 Timer Toggle On Overflow Register 1 (TTOV)Read: AnytimeWrite: Anytime5TSFRZTimer Stops While in Freeze Mode0 Allows the timer counter to continue running while in freeze mode.1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.TSFRZ does not stop the pulse accumulator.4TFFCATimer Fast Flag Clear All0 Allows the timer flag clearing to function normally.1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNTregister (0x0004, 0x0005) clears the TOF flag. This has the advantage of eliminating software overhead in aseparate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses.3PRNTPrecision Timer0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescalerselection.1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, andall bits.This bit is writable only once out of reset.Module Base + 0x00077 6 5 4 3 2 1 0R RESERVED RESERVED RESERVED RESERVED TOV3 TOV2 TOV1 TOV0WReset 0 0 0 0 0 0 0 0Figure 11-9. Timer Toggle On Overflow Register 1 (TTOV)Table 11-5. TTOV Field DescriptionsNote: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.Field Description3:0TOV[3:0]Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect whenin output compare mode. When set, it takes precedence over forced output compare0 Toggle output compare pin on overflow feature disabled.1 Toggle output compare pin on overflow feature enabled.Table 11-4. TSCR1 Field Descriptions (continued)Field Description
