Section number Title Page13.4.13 Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)............................................... 22813.5 Functional description...................................................................................................................................................23113.5.1 Access evaluation macro................................................................................................................................23113.5.2 Putting it all together and error terminations................................................................................................. 23313.5.3 Power management........................................................................................................................................ 23313.6 Initialization information.............................................................................................................................................. 23413.7 Application information................................................................................................................................................234Chapter 14Peripheral Bridge (AIPS-Lite)14.1 Chip-specific AIPS information................................................................................................................................... 23714.1.1 Instantiation information................................................................................................................................23714.1.2 Memory maps................................................................................................................................................ 23714.2 Introduction...................................................................................................................................................................23814.2.1 Features.......................................................................................................................................................... 23814.2.2 General operation........................................................................................................................................... 23814.3 Memory map/register definition................................................................................................................................... 23914.3.1 AIPS register descriptions..............................................................................................................................23914.4 Functional description...................................................................................................................................................28314.4.1 Access support............................................................................................................................................... 283Chapter 15Direct Memory Access Multiplexer (DMAMUX)15.1 Chip-specific DMAMUX information......................................................................................................................... 28515.1.1 Number of channels ...................................................................................................................................... 28515.1.2 DMA transfers via TRGMUX trigger............................................................................................................28515.2 Introduction...................................................................................................................................................................28515.2.1 Overview........................................................................................................................................................ 28615.2.2 Features.......................................................................................................................................................... 28615.2.3 Modes of operation........................................................................................................................................ 28715.3 Memory map/register definition................................................................................................................................... 287MWCT101xS Series Reference Manual, Rev. 3, 07/201910 NXP Semiconductors
