28.3.2 SRAM accessibilityBoth SRAM_L and SRAM_U have a frontdoor port and a backdoor port.The following table summarizes the master access to and performance of accesses to eachport. The following figure illustrates the master access.Table 28-3. SRAM accessibility and performanceSRAM region Frontdoor port Backdoor portMaster access Performance Master access PerformanceSRAM_L Cortex-M4F core codebusSingle-cycle access Non-core bus masters Minimum two cycles forread and one cycle forwriteSRAM_U Cortex-M4F coresystem busSingle-cycle access Non-core bus masters Minimum two cycles forread and one cycle forwriteCortex-M4F coreCode busSystem busSRAM controllerBackdoorSRAM_LSRAM_UCrossbar SwitchNon-core masterNon-core masterNon-core masterFrontdoorSystemMPUSystemMPUFigure 28-1. SRAM accessibilityThe following simultaneous accesses to SRAM_L and SRAM_U can occur:• Core code bus access to SRAM_L and core system bus access to SRAM_U• Core code bus access to SRAM_L and non-core bus master access to SRAM_U• Core system bus access to SRAM_U and non-core bus master access to SRAM_LThe following table illustrates these scenarios.Table 28-4. SRAM simultaneous accessesCore code bus access Core system bus access Non-core bus master accessSRAM_L SRAM_U —SRAM_L — SRAM_U— SRAM_U SRAM_LChapter 28 Memories and Memory InterfacesMWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 631
