41.5.24 Capture Test ModeThe Capture Test mode allows to test the CnV registers, the FTM counter and theinterconnection logic between the FTM counter and CnV registers.In this test mode, all channels must be configured for Input Capture Mode and FTMcounter must be configured to the Up counting.When the Capture Test mode is enabled (CAPTEST = 1), the FTM counter is frozen andany write to CNT register updates directly the FTM counter; see the following figure.After it was written, all CnV registers are updated with the written value to CNT registerand CHF bits are set. Therefore, the FTM counter is updated with its next valueaccording to its configuration. Its next value depends on CNTIN, MOD, and the writtenvalue to FTM counter.The next reads of CnV registers return the written value to the FTM counter and the nextreads of CNT register return FTM counter next value.FTM counter clockwrite to MODECAPTEST bitFTM counterwrite to CNTCHF bitCnVNote:- FTM counter is in free running- FTMEN = 1- FTM channel (n) is in Input Capture Mode0x0300 0x78ACset CAPTESTclear CAPTESTwrite 0x78AC0x10560x1053 0x10550x1054 0x78AC 0x78AD 0x78AE 0x78AF 0x78B0Figure 41-93. Capture Test Mode41.5.25 DMAThe channel generates a DMA transfer request according to DMA and CHIE bits. See thefollowing table.Functional DescriptionMWCT101xS Series Reference Manual, Rev. 3, 07/20191256 NXP Semiconductors
