• One output port, EWM_OUT_b, when asserted is used to reset or place the externalcircuit into safe mode.• One Input port, EWM_in, allows an external circuit to control the assertion of theEWM_OUT_b signal.18.2.2 Modes of OperationThis section describes the module's operating modes.18.2.2.1 Stop ModeWhen the EWM is in stop mode, the CPU refreshes to the EWM cannot occur. On entryto stop mode, the EWM's counter freezes.There are two possible ways to exit from Stop mode:• On exit from stop mode through a reset, the EWM remains disabled.• On exit from stop mode by an interrupt, the EWM is re-enabled, and the countercontinues to be clocked from the same value prior to entry to stop mode.Note the following if the EWM enters the stop mode during CPU refresh mechanism: Atthe exit from stop mode by an interrupt, refresh mechanism state machine starts from theprevious state which means, if first refresh command is written correctly and EWMenters the stop mode immediately, the next command has to be written within the next 15peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior toexecuting EWM refresh instructions.18.2.2.2 Debug ModeEntry to debug mode has no effect on the EWM.• If the EWM is enabled prior to entry of debug mode, it remains enabled.• If the EWM is disabled prior to entry of debug mode, it remains disabled.Chapter 18 External Watchdog Monitor (EWM)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 419
