48.3.1.21.2 DiagramBits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R CMPWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 048.3.1.21.3 FieldsField Function31-16—Reserved.15-0CMPTimer Compare ValueThe timer compare value is loaded into the timer counter when the timer is first enabled, when the timer isreset and when the timer decrements down to zero.In 8-bit baud counter mode, the lower 8-bits configure the baud rate divider equal to (CMP[7:0] + 1) * 2.The upper 8-bits configure the number of bits in each word equal to (CMP[15:8] + 1) / 2.In 8-bit PWM high mode, the lower 8-bits configure the high period of the output to (CMP[7:0] + 1) andthe upper 8-bits configure the low period of the output to (CMP[15:8] + 1).In 16-bit counter mode, the compare value can be used to generate the baud rate divider (if shift clocksource is timer output) to equal (CMP[15:0] + 1) * 2. When the shift clock source is a pin or trigger input,the compare register is used to set the number of bits in each word equal to (CMP[15:0] + 1) / 2.48.4 Functional description48.4.1 Clocking and Resets48.4.1.1 Functional clockThe FlexIO functional clock is asynchronous to the bus clock and can remain enabled inlow power modes. The FlexIO functional clock must be enabled before accessing anyFlexIO registers. Provided the FlexIO functional clock is at least two times faster than thebus clock, the CTRL[FASTACC] bit can be set to support fast register accesses.Functional descriptionMWCT101xS Series Reference Manual, Rev. 3, 07/20191542 NXP Semiconductors
