Table 37-4. WCT101xS register implementation (continued)Register/Offset WCT1014S WCT1015S WCT1016SaRA - aRP / 188 - 1C4SC1Q - SC1X /148 - 164RQ - RX / 1C8 - 1E4Reserved/NotimplementedAvailable/Implemented Available/ImplementedSC1Y - SC1AF / 168 -184RY - RAF / 1E8 - 204Reserved/NotImplementedReserved/Not Implemented Available/Implemented37.3 DMA Support on ADCApplications may require continuous sampling of the ADC (4K samples/sec) that mayhave considerable load on the CPU. Though using the Programmable Delay Block (PDB)to trigger the ADC may reduce some CPU load, the ADC supports DMA requestfunctionality for higher performance when the ADC is sampled at a very high rate or incases where the PDB is bypassed. The ADC can trigger the DMA (via DMA request)upon conversion completion.For most cases, the DMA request can be directly triggered from ADC conversioncompletion. The device also supports another way to trigger DMA: via the TRGMUX.The TRGMUX will provide user a more flexible DMA triggering scheme using softwarebased on different application requirements, for example, the DMA can be triggered aftermultiple ADC conversion completion instead of every ADC conversion completion.37.4 ADC Hardware Interleaved ChannelsOn devices with two ADCs, there are several special ADC channels which supporthardware interleave between multiple ADCs. Taking ADC0_SE4 and ADC1_SE14channels as an example, these two channels can work independently, but they can also behardware interleaved as following diagram. In the hardware interleaved mode, a signal onthe pin PTB0 can be sampled by both ADC0 and ADC1. The interleaved mode is enabledby SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits.The hardware interleave implementation on this device is as following:• ADC0_SE4 and ADC1_SE14 channels are interleaved on PTB0 pin• ADC0_SE5 and ADC1_SE15 channels are interleaved on PTB1 pin• ADC1_SE8 and ADC0_SE8 channels are interleaved on PTB13 pin• ADC1_SE9 and ADC0_SE9 channels are interleaved on PTB14 pinChapter 37 ADC ConfigurationMWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 973
