36.4 Modes of Operation36.4.1 Full Performance Mode (FPM)For the following Chip Power Modes, the internal voltage regulator is in full performancemode: HSRUN, RUN, STOP1, STOP2.36.4.2 Low Power Mode (LPM)For the following Chip Power Modes, the internal voltage regulator is in low powermode: VLPR and VLPS.36.5 Low Voltage Detect (LVD) SystemNOTEThe low voltage detect system (Low voltage detect flag, Lowvoltage warning flag and Low voltage detect reset generation)is disabled in low power mode.This device includes a system to guard against low voltage conditions. This protectsmemory contents and controls MCU system states during supply voltage variations. Thesystem is comprised of a power-on reset (POR) circuit and a LVD circuit with two trippoints. The LVD is disabled upon entering low power mode.Two flags are available to indicate the status of the low voltage detect system:• The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDFbit is set when the supply voltage falls below the trip point (VLVD). The LVDF bit iscleared by writing one to the LVDACK bit, but only if the internal supply hasreturned above the trip point; otherwise, the LVDF bit remains set. This flag getscleared on reset. The flag is only valid after the device has come out of the reset, atwhich point the flag will be set accordingly to the voltage level. If supply level ishigher than LVD threshold then this flag stay cleared, else this flag gets set.• The low voltage warning flag (LVWF) operates in a level sensitive manner. TheLVWF bit is set when the supply voltage falls below the selected monitor trip point(VLVW). The LVWF bit is cleared by writing one to the LVWACK bit, but only if theinternal supply has returned above the trip point; otherwise, the LVWF bit remainsset. This flag gets cleared on reset. The flag is only valid after the device has comeModes of OperationMWCT101xS Series Reference Manual, Rev. 3, 07/2019962 NXP Semiconductors
