Chapter 33Quad Serial Peripheral Interface (QuadSPI)Chip-specific QuadSPI information33.1.1 OverviewWCT1016S has one instance of QuadSPI. Other products in the WCT101xS series do nothave QuadSPI.See the device Data Sheet for details about target frequencies.The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to externalserial flash device. It supports SDR and HyperRAM modes upto 4 and 8 bidirectionaldata lines respectively.NOTEThe following are not supported:• AHB Write• Data learning feature• Breakpoint and Watchpoint memory regions33.1.2 Memory size requirementQuadSPI memory size requirement for AHB Buffers is : 128x64 , i.e. 1 KB.33.1.3 QuadSPI register reset valuesTable 33-1. QuadSPI register reset valuesRegister Reset valueModule Configuration Register (QuadSPI_MCR) 000F_400CTable continues on the next page...33.1MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 819
