Chapter 46Low Power Inter-Integrated Circuit (LPI2C)Chip-specific LPI2C information46.1.1 Instantiation informationThe following table summarizes the implementation of this module for each chip in theproduct series.Table 46-1. LPI2C configurationChip Instances TX FIFO (word) RX FIFO (word) SMBus Slave modeenableWCT1014S LPI2C0 4 4 Yes YesWCT1015S LPI2C0 4 4 Yes YesWCT1016S LPI2C0 4 4 Yes YesLPI2C1 4 4 Yes YesLow leakage and Wait mode is not supported in this device. See Module operation inavailable power modes for details on available power modes.HS-Mode (baud-rates above 400 kbps) is not supported on this device.The LPI2C module includes SMBus support and DMA support.NOTE• Only SIRC is the valid clock source in VLP modes. As theSIRC supports the LPI2C data rates, it is recommended touse SIRC for LPI2C to avoid clock reconfiguration andswitching times.46.1MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 1409
