3.5 Private Peripheral Bus (PPB) memory mapThe PPB is part of the defined Arm bus architecture and provides access to selectprocessor-local modules. These resources are only accessible from the core; other systemmasters do not have access to them.Table 3-3. PPB memory mapSystem 32-bit address range Resource0xE000_0000–0xE000_0FFF Instrumentation Trace Macrocell (ITM)0xE000_1000–0xE000_1FFF Data Watchpoint and Trace (DWT)0xE000_2000–0xE000_2FFF Flash Patch and Breakpoint (FPB)0xE000_3000–0xE000_DFFF Reserved0xE000_E000–0xE000_EFFF System Control Space (SCS) (for NVIC and FPU0xE000_F000–0xE003_FFFF Reserved0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU)0xE004_1000–0xE004_1FFF Reserved0xE004_2000–0xE004_2FFF Reserved0xE004_3000–0xE004_3FFF Reserved0xE004_4000–0xE007_FFFF Reserved0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM)0xE008_1000–0xE008_1FFF Reserved0xE008_2000–0xE008_2FFF Cache Controller (LMEM)0xE008_3000–0xE00F_EFFF Reserved0xE00F_F000–0xE00F_FFFF Arm Core ROM Table1 - allows auto-detection of debug components1. The Arm Core ROM table is optionally required by Arm CoreSight debug infrastructure to discover the components on thechip. This ROM table has no any relationship with the MCU Boot ROM.3.6 Aliased bit-band regionsThe SRAM_U, AIPS-Lite, and general purpose input/output (GPIO) module resourcesreside in the Cortex-M4F processor bit-band regions.The processor also includes two 32 MB aliased bit-band regions associated with the two1 MB bit-band spaces. Each 32-bit location in the 32 MB space maps to an individual bitin the bit-band region. A 32-bit write in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.Bit 0 of the value written to the alias region determines what value is written to the targetbit:Private Peripheral Bus (PPB) memory mapMWCT101xS Series Reference Manual, Rev. 3, 07/201968 NXP Semiconductors
