• Selectable clock source for digital input filter with a five bit resolution on filtersize• Functional in all digital pin multiplexing modes• Port control• Individual pull control fields with pullup, pulldown, and pull-disable support• Individual drive strength field supporting high and low drive strength• Individual input passive filter field supporting enable and disable of theindividual input passive filter• Individual mux control field supporting analog or pin disabled, GPIO, and up tosix chip-specific digital functions• Pad configuration fields are functional in all digital pin muxing modes.10.3.2 Modes of operation10.3.2.1 Run modeIn Run mode, the PORT operates normally.10.3.2.2 Wait modeIn Wait mode, PORT continues to operate normally and may be configured to exit theLow-Power mode if an enabled interrupt is detected. DMA requests are still generatedduring the Wait mode, but do not cause an exit from the Low-Power mode.10.3.2.3 Stop modeIn Stop mode, the PORT can be configured to exit the Low-Power mode via anasynchronous wake-up signal if an enabled interrupt is detected.In Stop mode, the digital input filters are bypassed unless they are configured to run fromthe LPO clock source.10.3.2.4 Debug modeIn Debug mode, PORT operates normally.Chapter 10 Port Control and Interrupts (PORT)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 163
