FTM input clockCNTchannel (n) inputCHF bitC(n)V XX 0x27selected channel (n) input event: rising edgeNOTEChannel (n) input after its synchronizer and filterMOD = 0xFFFFCNTIN = 0x0000PS[2:0] = 3'b000ICRST = 1'b1... 0x27 ...0x00 0x01 0x02 0x030x260x250x240x230x220x210x20Figure 41-20. Example of the Input Capture mode with ICRST = 1NOTE• It is expected that the ICRST bit be set only when thechannel is in input capture mode.• If the FTM counter is reset because the channel is in inputcapture mode with ICRST = 1, then the prescaler counter(Prescaler) is also reset.41.5.6 Output Compare modeThe Output Compare mode is selected when:• DECAPEN = 0• MCOMBINE = 0• COMBINE = 0• CPWMS = 0, and• MSB:MSA = 0:1In Output Compare mode, the FTM can generate timed pulses with programmableposition, polarity, duration, and frequency. When the counter matches the value in theCnV register of an output compare channel, the channel (n) output can be set, cleared, ortoggled.When a channel is initially configured to Toggle mode, the previous value of the channeloutput is held until the first output compare event occurs.The CHF bit is set and the channel (n) interrupt is generated if CHIE = 1 at the channel(n) match (FTM counter = CnV).Chapter 41 FlexTimer Module (FTM)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 1203
