Section number Title Page20.2.1 Overview........................................................................................................................................................ 44320.2.2 Features.......................................................................................................................................................... 44420.3 ERM register descriptions.............................................................................................................................................44420.3.1 ERM Memory map........................................................................................................................................ 44420.3.2 ERM Configuration Register 0 (CR0)........................................................................................................... 44520.3.3 ERM Status Register 0 (SR0)........................................................................................................................ 44720.3.4 ERM Memory n Error Address Register (EAR0 - EAR1)............................................................................ 44920.4 Functional description...................................................................................................................................................45020.4.1 Single-bit correction events........................................................................................................................... 45020.4.2 Non-correctable error events..........................................................................................................................45120.5 Initialization.................................................................................................................................................................. 452Chapter 21Watchdog timer (WDOG)21.1 Chip-specific WDOG information................................................................................................................................45321.1.1 WDOG clocks................................................................................................................................................ 45321.1.2 WDOG low-power modes............................................................................................................................. 45321.1.3 Default watchdog timeout ............................................................................................................................. 45421.1.4 Watchdog Timeout Reaction......................................................................................................................... 45421.2 Introduction...................................................................................................................................................................45521.2.1 Features.......................................................................................................................................................... 45521.2.2 Block diagram................................................................................................................................................ 45621.3 Memory map and register definition.............................................................................................................................45621.3.1 WDOG register descriptions.......................................................................................................................... 45621.4 Functional description...................................................................................................................................................46321.4.1 Clock source...................................................................................................................................................46321.4.2 Watchdog refresh mechanism........................................................................................................................ 46421.4.3 Configuring the Watchdog.............................................................................................................................46621.4.4 Using interrupts to delay resets...................................................................................................................... 46721.4.5 Backup reset................................................................................................................................................... 467MWCT101xS Series Reference Manual, Rev. 3, 07/201914 NXP Semiconductors
