19.2.2 FeaturesThe EIM includes these features:• Supports 2 error injection channels• Protection against accidental enable and reconfiguration error injection function viatwo-stage enable mechanism19.3 EIM register descriptionsThe EIM provides an IPS programming model mapped to an on-platform peripheral slot.Programming model accessAll system bus masters can access the programming model:• Only in supervisor mode• Using only 32-bit (word) accessesAny of the following attempted references to the programming model generates an IPSerror termination:• In user mode• Using non-32-bit access sizes• To undefined (reserved) addressesAttempted updates to the programming model while the EIM is in the midst of anoperation result in non-deterministic behavior.Error injection channel descriptor: function and structureEach error injection channel descriptor:• Specifies a mask that defines which bits of the read data and checkbit bus from targetRAM are inverted on a read access.• Consists of a 128-bit (16-byte) structure, composed of four 32-bit words, in the EIMprogramming model.• The first word, Word0 (EICHDn_WORD0), defines the checkbit mask. SeeError Injection Channel Descriptor n, Word0 for details.• The remaining words, Word1-3 (EICHDn_WORD1-3), define the data mask.Word2 and Word3 are used only when required by the total width of theChapter 19 Error Injection Module (EIM)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 433
