The hardware trigger select event, ADHWTSn, must be set prior to the receipt of theADHWT signal. If these conditions are not met, the converter may ignore the trigger oruse an incorrect configuration. If a hardware trigger select event is asserted during aconversion, it must stay asserted until the end of current conversion and remain set untilthe receipt of the ADHWT signal to trigger a new conversion. The channel and statusfields selected for the conversion depend on the active trigger select signal:• ADHWTSA active selects SC1A.• ADHWTSn active selects SC1n.When the conversion is completed, the result is placed in the Rn registers associated withthe ADHWTSn received. For example:• ADHWTSA active selects RA register• ADHWTSn active selects Rn registerThe conversion complete flag associated with the ADHWTSn received, that is,SC1n[COCO], is then set and an interrupt is generated if the respective conversioncomplete interrupt has been enabled, that is, SC1[AIEN]=1.38.5.4 Conversion controlConversion mode is selected by configuring CFG1[MODE].Conversions can be initiated by a software or hardware trigger.In addition, the ADC module can be configured for:• Low-power operation• Long sample time• Continuous conversion• Hardware average• Automatic compare of the conversion result to a software-determined compare value38.5.4.1 Initiating conversionsA conversion is initiated:• Following a write to SC1A, if software-triggered operation is selected, that is, whenSC2[ADTRG] = 0.• Following a hardware trigger, or ADHWT event, if hardware-triggered operation isselected, that is, SC2[ADTRG] = 1, and a hardware trigger select event, ADHWTSn,has occurred. The channel and status fields that are selected depend on the activetrigger select signal:Chapter 38 Analog-to-Digital Converter (ADC)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 1039
