49.1.3 FlexCAN external time tickOn this device, LPIT channel 0 trigger output acts as external time tick source forFlexCAN0.49.1.4 FlexCAN InterruptsThe FlexCAN has multiple sources of interrupt requests. However, some of these sourcesare OR'd together to generate a single interrupt request. See below for the mapping of theindividual interrupt sources to the interrupt request:Table 49-2. FlexCAN InterruptsRequest For CAN with FD For CAN without FDMessage Buffer Message buffers 0-31 Message buffers 0-15Bus off Bus off Bus offError • Bit1 error or Bit1 error in DataPhase of CAN FD frames• Bit0 error or Bit0 error in DataPhase of CAN FD frames• Acknowledge error• Cyclic redundancy check error orCyclic redundancy in Data Phaseof CAN FD frames• Form error or Form error in DataPhase of CAN FD frames• Stuffing error or Stuffing error inData Phase of CAN FD frames• Transmit error warning• Receive error warning• CAN-FD error• Bit1 error• Bit0 error• Acknowledge error• Cyclic redundancy check (CRC)error• Form error• Stuffing error• Transmit error warning• Receive error warningTransmit Warning Transmit Warning Transmit WarningReceive Warning Receive Warning Receive Warning49.1.5 FlexCAN Operation in Low Power ModesThe FlexCAN module is operational in VLPR mode. With the 4 MHz system clock (inVLPR mode), the fastest supported FlexCAN transfer rate is 250 kbps. The bit timingparameters in the module must be adjusted for the new frequency, but full functionality ispossible.See Module operation in available power modes for details on available power modes.Chip-specific FlexCAN informationMWCT101xS Series Reference Manual, Rev. 3, 07/20191564 NXP Semiconductors
