A module capable of providing an asynchronous interrupt to the device takes the deviceout of STOP mode and returns the device to normal RUN mode. Refer to the device'sPower Management chapter for peripheral, I/O, and memory operation in STOP mode.When an interrupt request occurs, the CPU exits STOP mode and resumes processing,beginning with the stacking operations leading to the interrupt service routine.A system reset will cause an exit from STOP mode, returning the device to normal RUNmode via an MCU reset.35.4.4.2 Very-Low-Power Stop (VLPS) modeThe two ways in which VLPS mode can be entered are listed here.• Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in theSystem Control Register in the Arm core while the MCU is in VLPR mode andPMCTRL[STOPM] = 010 or 000.• Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in theSystem Control Register in the Arm core while the MCU is in normal RUN modeand PMCTRL[STOPM] = 010. When VLPS is entered directly from RUN mode, exitto VLPR is disabled by hardware and the system will always exit back to RUN.In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR.A module capable of providing an asynchronous interrupt to the device takes the deviceout of VLPS and returns the device to VLPR mode.A system reset will also cause a VLPS exit, returning the device to normal RUN mode.35.4.5 Debug in low power modesWhen the MCU is secure, the device disables/limits debugger operation. When the MCUis unsecure, the Arm debugger can assert two power-up request signals:• System power up, via SYSPWR in the Debug Port Control/Stat register• Debug power up, via CDBGPWRUPREQ in the Debug Port Control/Stat registerWhen asserted while in RUN or VLPR, the mode controller drives a correspondingacknowledge for each signal, that is, both CDBGPWRUPACK and CSYSPWRUPACK.When both requests are asserted, the mode controller handles attempts to enter STOP andVLPS by entering an emulated stop state. In this emulated stop state:• the regulator is in run regulation,• the SCG-generated clock source is enabled,Functional descriptionMWCT101xS Series Reference Manual, Rev. 3, 07/2019958 NXP Semiconductors
