FTM counterCNTINC(n+1)Vnot fully 0% duty cyclechannel (n) outputwith ELSB:ELSA = 1:0not fully 100% duty cyclechannel (n) outputwith ELSB:ELSA = X:1MOD = C(n)VFigure 41-45. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD)FTM counter100% duty cyclechannel (n) outputwith ELSB:ELSA = 1:0channel (n) outputwith ELSB:ELSA = X:1 0% duty cycleMODC(n)V = CNTINC(n+1)VFigure 41-46. Channel (n) output if (C(n)V = CNTIN) and (C(n+1)V > MOD)41.5.9.1 Asymmetrical PWMIn Combine mode and Modified Combine PWM Mode, the PWM first edge (channel (n)match: FTM counter = C(n)V) is independent of the PWM second edge (channel (n+1)match: FTM counter = C(n+1)V).41.5.10 Modified Combine PWM ModeThe Modified Combine PWM mode is selected when:• QUADEN = 0• DECAPEN = 0Functional DescriptionMWCT101xS Series Reference Manual, Rev. 3, 07/20191216 NXP Semiconductors
