Chapter 34Power Management34.1 IntroductionThis chapter describes the various chip power modes and functionality of the individualmodules in these modes.34.2 Power modes descriptionThe Power Management Controller (PMC) provides multiple power options allowingusers to optimize power consumption for the level of functionality needed.Depending on the stop requirements of the user application, a variety of stop modes areavailable that provide state retention, partial power down or full power down of certainlogic and/or memory. I/O states are maintained during all power modes. The followingtable compares the various power modes available.For Run and Very Low Power Run (VLPR) modes there are corresponding Stop modes.Stop modes (VLPS, STOP1, STOP2) are similar to Arm sleep deep mode. VLPRoperating mode can reduce runtime power when maximum bus frequency is not requiredto support application needs.This chip cannot enter a stop mode directly from High Speed Run (HSRUN) mode. Toenter a stop mode from HSRUN, the chip must first transition to Normal Run mode.After that, it can enter a stop mode.The two primary modes of operation are Run, Stop. The Wait For Interrupt (WFI)instruction invokes Stop modes for the chip. The available power modes allow anapplication to consume only the power that is necessary for execution.MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 929
