QUADSPIClock GenSamplingSerial FlashClockDataOutSCK - Serial Flash ClockSI_IO[0:7] - Serial Flash Data15243Figure 33-8. Serial Flash Sampling Clock OverviewThe rising edge of the internal reference clock is taken as timing reference for the dataoutput of the serial flash. After a time of tDel,total the data arrives at the internal samplingstage of the QuadSPI module. According to the Serial Flash Sampling Clock Overviewfigure, the following parts of the delay chain contribute to tDel,total:1. Output delay of the serial flash clock output of the device containing the QuadSPImodule2. Wire delay of application/PCB from the device containing the QuadSPI module tothe external serial flash device3. Clock to data out delay of the external serial flash device, including input and outputdelays4. Wire delay of application/PCB from the external serial flash device to the devicecontaining the QuadSPI module5. Device delay corresponding to the input dataNOTEThe amount of total delay tDel,total is specific to thecharacteristics of the actual implementation. Also, the serialflash device clock (SCK) is inverted with respect to theQuadSPI internal reference clock.33.12.2 Supported read modesSome modes listed here may not be available on this chip. See the chip-specific QuadSPIinformation for the read modes that this chip supports.Sampling of Serial Flash Input DataMWCT101xS Series Reference Manual, Rev. 3, 07/2019922 NXP Semiconductors
