commands will lead to Bank1. The extended address register needs to be update withthe respective value for access to other banks. This effectively converts the legacy24-bit address command into 32-bit address commands.• Separation of address into row and column addressThis mode has been introduced for flashes which needs addresses segregated intoRow and Column. The value in QSPI_SFACR[CAS] defines the width of the columnaddress required by a flash. The actual address to be provided will be derived fromthe incoming address in case of AHB initiated transactions and the value of SFAR incase of IPS initiated transactions , if QSPI_SFACR[CAS] is set to 0, else the actualaddress will take CAS into consideration. If QSPI_SFACR[CAS] is 3 then bits 26-3of the address programmed are sent to flash as it page address in case flash isoperating in 24bit mode and bits 2-0 are sent as its column address. If a flashrequirement for column address is less than the number of pads in which address hasto be sent than the remaining bits are appended with 0 by QuadSPI. The user mustprogram the operand value in CADDR and CADDR_DDR command accordingly. Itmust be ensured that the total number of address bits request by flash as its page andcolumn address must not be more than 32 bits.• Word addressable mode for FlashThis mode has been introduced for flashes which has word addressable memory i.e.each address of the flash contains one word (two bytes) of data. The QSPI_SFACR[WA] is set to 1 to enter this mode. QuadSPI internally divides the incoming addressin the AHB bus or the address in the QSPI_SFAR to map it to a valid flash location.For example, if the incoming address is 0x2004, the controller re-maps this addressto access the flash location 0x1002. If not in this mode, the incoming address 0x2004will be mapped to flash location 0x2004.33.7.3 HyperRAM SupportThe QuadSPI supports HyperRAM memories and by virtue of this protocol, QuadSPIsupports the following functionalities.• Bidirectional data strobe/read write data strobe (RWDS)• When QuadSPI is configured to use the HyperRAM mode, the RWDS padshould be pulled down.• Variable refresh latency• If QuadSPI_MCR[VAR_LAT_EN] field is set, based on the status of RWDSfrom HyperRAM during Command/Address phase, QuadSPI includes additionalinitial access latency. If RWDS is high, QuadSPI will include twice + 1 theFunctional DescriptionMWCT101xS Series Reference Manual, Rev. 3, 07/2019904 NXP Semiconductors
