13.4.6 Region Descriptor 0, Word 1 (RGD0_WORD1)13.4.6.1 OffsetRegister OffsetRGD0_WORD1 404h13.4.6.2 FunctionThe second word of the region descriptor defines the 31-modulo-32 byte end address ofthe memory region. Writes to this register clear the region descriptor’s valid bit(RGDn_WORD3[VLD]).13.4.6.3 DiagramBits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R ENDADDRWReset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R ENDADDR ReservedWReset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 113.4.6.4 FieldsField Function31-5ENDADDREnd AddressDefines the most significant bits of the 31-modulo-32 byte end address of the memory region.NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR.4-0—ReservedMPU register descriptionsMWCT101xS Series Reference Manual, Rev. 3, 07/2019214 NXP Semiconductors
