When a rising edge occurs in the channel (n) input signal, the FTM counter value iscaptured into channel (n) capture buffer. The channel (n) capture buffer value istransferred to C(n)V register when a falling edge occurs in the channel (n) input signal.C(n)V register has the FTM counter value when the previous rising edge occurred, andthe channel (n) capture buffer has the FTM counter value when the last rising edgeoccurred.When a falling edge occurs in the channel (n) input signal, the FTM counter value iscaptured into channel (n+1) capture buffer. The channel (n+1) capture buffer value istransferred to C(n+1)V register when the C(n)V register is read.In the following figure, the read of C(n)V returns the FTM counter value when the event1 occurred and the read of C(n+1)V returns the FTM counter value when the event 2occurred.read C(n+1)VFTM counterchannel (n) input(after the filterchannel input)channel (n)capture bufferC(n)VC(n+1)Vchannel (n+1)capture bufferevent 1 event 2 event 3 event 4 event 5 event 6 event 7 event 8 event 91 2 3 4 5 6 7 8 991 3 756 84221 3 5 7read C(n)VFigure 41-100. Dual Edge Capture mode read coherency mechanismC(n)V register must be read prior to C(n+1)V register in dual edge capture one-shot andcontinuous modes for the read coherency mechanism works properly.41.5.27 Quadrature Decoder ModeThe quadrature decoder mode is enabled if QUADEN = 1. The quadrature decoder modeuses the input signals phase A and B to control the FTM counter increment anddecrement.Chapter 41 FlexTimer Module (FTM)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 1265
