21.5.3 Configure WatchdogThe watchdog can be configured once by set the WDOG_CS[UPDATE]=0. After that,the watchdog cannot be reconfigured until a reset. If set WDOG_CS[UPDATE]=1 whenconfiguring the watchdog, the watchdog can be reconfigured without forcing a reset. Thefollowing example code shows how to configure the watchdog without window mode,clock source as LPO, interrupt enabled and timeout value to 256 clocks. The code snippetbelow shows an example for 32-bit write.Configure onceDisableInterrupts; // disable global interruptWDOG_CNT = 0xD928C520; //unlock watchdogwhile(WDOG_CS[ULK]==0); //wait until registers are unlockedWDOG_TOVAL = 256; //set timeout valueWDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) |WDOG_CS_WIN(0) | WDOG_CS_UPDATE(0);while(WDOG_CS[RCS]==0); //wait until new configuration takes effectEnableInterrupts; //enable global interruptConfigure for reconfigurableDisableInterrupts; //disable global interruptWDOG_CNT = 0xD928C520; //unlock watchdogwhile(WDOG_CS[ULK]==0); //wait until registers are unlockedWDOG_TOVAL = 256; //set timeout valueWDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) |WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1);while(WDOG_CS[RCS]==0); //wait until new configuration takes effectEnableInterrupts; //enable global interrupt21.5.4 Refreshing the WatchdogTo refresh the watchdog and reset the watchdog counter to zero, a refresh sequence isrequired. The code snippet below shows an example for 32-bit write.DisableInterrupts; // disable global interruptWDOG_CNT = 0xB480A602; // refresh watchdogEnableInterrupts; // enable global interruptChapter 21 Watchdog timer (WDOG)MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 471
