Chapter 43Low Power Timer (LPTMR)Chip-specific LPTMR information43.1.1 Instantiation InformationWCT101xS contains one LPTMR module with either a 1 channel 16-bit time counter or a1 channel 16-bit pulse counter.43.1.1.1 LPT/HSCMP0 pulse countingLPTMR_ALT0 input is the selectable source to count pulses resulting from HSCMP0Output (LPT_ALT0 = HSCMP0 Output) via TRGMUX.NOTE• Low leakage mode and Wait mode are not supported in thisdevice. See Module operation in available power modes fordetails on available power modes.• For LPTMR_PSR[PCS] bit options refer to table:Peripheral module clocking in section Module clocks.• fLPTMR referred in the chapter refers to fBUS parameter inthe datasheet43.1.2 LPTMR pulse counter input optionsThe LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode.The following table shows the chip-specific input assignments for this bitfield.43.1MWCT101xS Series Reference Manual, Rev. 3, 07/2019NXP Semiconductors 1335
