channel's data mask. See Error injection channel descriptor: DATA_MASKdetails and the individual registers' descriptions.The multiple channel descriptors are organized sequentially.Error injection channel descriptor: DATA_MASK detailsFor each channel: The following table shows the total width of DATA_MASK and thedistribution of its bits across the WORD registers.Channel DATA_MASK totalwidth (bits)Specific bits of DATA_MASK inWORD1 WORD2 WORD30 32 31-0 — —1 32 31-0 — —19.3.1 EIM Memory mapEIM base address: 4001_9000hOffset Register Width(In bits)Access Reset value0h Error Injection Module Configuration Register (EIMCR) 32 RW 0000_0000h4h Error Injection Channel Enable register (EICHEN) 32 RW 0000_0000h100h Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0) 32 RW 0000_0000h104h Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1) 32 RW 0000_0000h200h Error Injection Channel Descriptor n, Word0 (EICHD1_WORD0) 32 RW 0000_0000h204h Error Injection Channel Descriptor n, Word1 (EICHD1_WORD1) 32 RW 0000_0000h19.3.2 Error Injection Module Configuration Register (EIMCR)19.3.2.1 OffsetRegister OffsetEIMCR 0hEIM register descriptionsMWCT101xS Series Reference Manual, Rev. 3, 07/2019434 NXP Semiconductors
